The disclosure relates generally to placement-driven generation of error detecting structures in integrated circuits, and more specifically, to adding parity protection to control logic latches using physical design feedback to cluster unprotected latches into groups.
In general, conventional computing systems provide some level of error protection of single event upsets in order to ensure data integrity, to prevent the conventional computing systems from entering an illegal state, and to control resource availability. To this end, data is protected by parity or error-detecting/correcting mechanisms, and control latches can be protected with parity protection. It is preferred that any non-functional additions to an integrated circuit, such as those for error protection, have a minimal impact on timing, power consumption, and space, so as to not detract from the overall performance of the conventional computing systems. However, the error protection by the conventional computing systems is far from being optimized to ensure this minimal impact.